(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming DRAM devices.
(2) Description of Prior Art
Computer memory consist of vast arrays of storage cells which can be addressed by wordlines and bitlines. The most commonly used cell design used in current dynamic random access memories(DRAMS) comprise a transfer gate(usually an MOS field-effect-transistor(MOSFET) and a storage node consisting of a capacitor. DPAM cells are, by necessity of high density requirements, of the simplest design possible and to this end, the MOSFET-capacitor combination serves quite well.
The quest for miniaturization and the increasing demand for higher and higher densities of memory cells has resulted in many design variations of these simple MOSFET memory cells. One such design, referred to as the stacked capacitor cell(STC) DRAM, lends itself particularly well to extensive miniaturization within the framework of MOSFET technology, while at the same time maintaining adequate storage capability.
Miniaturization of the MOSFET has led to current DRAM designs using sub-half-micron ground rules. The DRAM capacitor, which resides atop the source diffusion of the MOSFET in the STC design, has been modified considerably over the last five years in order to keep up with the decreasing area available to it. Thus, much attention has been given to designing the capacitor in a smaller and smaller physical area without sacrificing capacitance.
An early DRAM cell design is illustrated in cross section by FIG. 1. The silicon wafer substrate 10 contains the source 14 and the drain 16 diffusions for the MOSFET whose polysilicon gate 18a is part of a word line extending perpendicular to the page. The wordline 18b forms the gates of other MOSFETs above and below the plane of the page. The polysilicon bottom plate of the storage capacitor 22 lies over an insulating layer 20 and is makes electrical contact to the source 14. The upper plate of the capacitor 26 rests upon the capacitors dielectric layer 24 and is covered by insulating layer 28. The bitline 30 is connected to the drain of the MOSFET.
Subsequent designs first by Kurosawa et.al. U.S. Pat. No. 4,951,175(1990) and later by Jin et.al. U.S. Pat. No. 5,216,267(1993) developed the concept of forming the lower electrode by first depositing a thick layer of polysilicon over the first insulating layer, then opening the source contact, and finally depositing a thinner polysilicon layer. In this way they were able to obtain some additional capacitor plate area as well as provide better control over the contact opening to the MOSFET source. The details of Jin et.al.s version is depicted in FIG. 2. This version is basically similar to that of Kurosawa et.al. except for a modification within the circle 34 and the addition of a flattening layer of borophosphosilicate glass(BPSG) 32 the purpose of which is to provide a gentler slope for the bitline 30.
Nagasawa et.al. U.S. Pat. No. 5,444,653(1995) took this concept a step further by making the first polysilicon layer 22 of the lower capacitor plate even thicker (6,000 Angstroms) and folding the capacitor down in the center(FIG.3) to make even greater plate area gains. In addition, by using a two-step etching procedure to form the contact opening D, the insulator spacing between the polysilicon gates and the capacitor contact (B) was improved. A further benefit achieved by this innovation was to reduce the danger of dopant encroachment from the polysilicon at the contact into the lightly-doped(LDD) region 14a of the source 14. The etching procedure utilizes oxide sidewalls and a layer of silicon nitride 21 as an etch stop.
Both Jin et.al. and Nagasawa et.al. provide n+ doping for both first and second layers of polysilicon which form the bottom plate of the capacitor. Kurosawa et.al. do not indicate a method of doping of the first(thicker) layer but do state that the second(thinner) layer is deposited about 500 Angstroms thick and that an ion implantation of arsenic takes place to a depth comparable to the thickness of the layer. They suggest 1.times.10.sup.16 cm.sup.2 at 60 keV which places the implant at a depth of about 400 Angstroms.
Motonami, et.al. U.S. Pat. No. 5,309,023(1994), like Nagasawa et.al., consider the risks of dopant encroachment from the DRAM capacitor lower plate contacts. They cite misalignment as a potential cause for this infiltration in particular into the LLD region. The increased concern for such encroachment is a direct consequence of continuing shrinkage of device design parameters which dictate very shallow junctions and tight alignment tolerances. The sub-half-micron design features of today demand a greater inclination to avoid potential device active area disruptions by subsequent processing. At the same time, the requirements for a stable, low-resistance(Ohmic) contact, become more sacrosanct. To this end, the introduction of additional dopant by implant at the capacitor lower plate source contact imposes risk. In particular, when very shallow junctions are involved, encroachment of the implant into the junction region is difficult to avoid.